Ferroelectric memory devices use the polarization of ferroelectric materials to store data in a non-volatile manner when power is removed. The polarization of the ferroelectric materials can be set and reversed by applying an external electrical field. The ferroelectric materials can then retain their polarization after the electric field is removed.
Ferroelectric memory devices may operate with low voltages (e.g., less than 5V), high speed (e.g., about several nano-seconds), and low current (e.g., less than 1 microampere standby current). Because of these characteristics, ferroelectric memory devices may be regarded as a next-generation type of non-volatile memory. As with all types of non-volatile memories, it can be important to obtain highly integrated ferroelectric memory devices.
Various cell structures of the ferroelectric memory devices have been suggested. For example, a first structure is a 1TC structure in which a unit cell consists of one transistor and one capacitor, and a second structure is a 2TC in which a unit cell consists of two transistors and two capacitors. Some early ferroelectric memory devices used the 2TC structure, such as described in U.S. Pat. No. 4,873,664. Because of the need for increased integration, the, 1TC structure, such as described in U.S. Pat. No. 5,978,251, became more widely used. As with DRAMs, bit line structures are classified into shared or open types (See U.S. Pat. No. 6,137,711) and folded type (See U.S. Pat. No. 6,151,243) according to the bit line structure for sensing data. A reading operation may be performed by applying a predetermined voltage pulse to one ferroelectric capacitor electrode opposite to the transistor via an interconnection (a plate line).
In this case, to fabricate high-integration ferroelectric memory device, preferably, one plate line may be connected to several capacitors. However, a ferroelectric layer of the ferroelectric capacitor can have several hundred or several thousand dielectric constants as compared with a dielectric layer used in DRAM. Accordingly, the number of capacitor that can be connected to one plate line can be limited. When several capacitors are connected to the plate line, the voltage pulse signal applied to the plate line exhibits a resistive-capacitive (RC) delay. As a result, a signal delay occurs which lowers the operational speed of the device and lowers the voltage applied to the ferroelectric capacitor. Because the number of ferroelectric capacitors connected to one plate line may be limited, circuits for selecting plate lines can increase, thereby increasing an associated chip size.
FIG. 1 is a plan view of the ferroelectric memory device applied to the shared bit line structure in conventional 1TC memory cell. FIG. 2 is an equivalent circuit of FIG. 1.
Referring to FIG. 1, several active regions 105, which are electrically insulated by an isolation region 103, are arranged along row and column directions in two-dimensions. Word lines 107 run along the row direction and are orthogonal to each of the active regions. A couple of word lines cross each of the active regions. Accordingly, each of the active regions may be classified as three parts, a drain region provided by the active region between a couple of the word lines, and two source regions provided by the active regions on both sides of a couple of the word lines. Bit lines 111a and 111b run between the active regions and are orthogonal to the word lines 107. Each of the bit lines is electrically connected through a drain contact pad 109b to the drain region. The ferroelectric capacitors 113c11, 113c12, 113c21, 113c22, 113c31, 113c32, 113c41, 113c42 are electrically connected through a source contact pad 109a to the source region corresponding to the ferroelectric capacitors 113. Plate lines 115a through 115d are parallel to the word line 107 and orthogonal to the bit line 111. Each of the plate lines 1105a-d is electrically connected to each of the capacitors along a column direction. As shown, plate line 115a is electrically connected to the ferroelectric capacitors 113c11, 113c12.
In the ferroelectric memory device having a conventional shared bit line structure, each of the plate lines is electrically connected to several ferroelectric capacitors along a column and insulated from the ferroelectric capacitors arranged along neighboring columns. As shown, the plate line 115a is electrically connected to the ferroelectric capacitors 113c11 and 113c12 arranged along the same column. Ferroelectric capacitors 113c21 and 113c22 arranged along the same column are electrically connected to the plate line 115b. Additionally, each of the bit lines control operation of the ferroelectric capacitors arranged along a row. As shown, the bit line 111a controls operation of the ferroelectric capacitors 113c11, 113c12, 113c31 and 113c41 in the same row.
Referring to FIG. 2, unit memory cell MC0 includes transistor N0 and ferroelectric capacitor CF0. The gate of the transistor N0 is connected to the word line WLi, the source is connected to the bit line BLi and the drain is connected to one electrode of the ferroelectric capacitor CF0. The other electrode of the ferroelectric capacitor is connected to the plate line PLi.
Memory cells MC0 are arranged in matrix shape. Memory cells connected to the same bit line are connected to each different plate line PLi (i numbered plate line) and PLi+1 respectively.
FIG. 3 is plan view of a ferroelectric memory device having a folded bit line structure in a conventional memory cell array having a 1TC structure. FIG. 4 is an equivalent circuit of FIG. 3.
Referring to FIG. 3, active regions 105 partially overlap. Each of the active regions of even numbered rows partially overlap two adjacent active regions of odd numbered rows. A couple of the word lines 107 extend along columns and are on each of the active regions. Accordingly, each of the active regions may be classified into three parts, a drain region between a couple of the word lines, and two source regions on both sides of the word lines. Bit lines 111 cross above isolation regions 103 between the active regions and are orthogonal to the word lines. Each of the bit lines is electrically connected through the drain contact pad 109b to the drain region. Ferroelectric capacitors 113 are electrically connected through source contact pads 109a to the source region corresponding to the ferroelectric capacitors. Plate lines 115 are parallel to the word line 107 and orthogonal to the bit line 111. Each of the plate lines 115 is electrically connected to each of the capacitors along a column. In contrast to the ferroelectric memory device having shared bit line structure, the active regions herein partially overlap. Accordingly, the ferroelectric capacitors in a column under a certain plate line are operated by the word lines in different columns.
Referring to FIG. 4, one memory cell is operated by two neighboring bit lines BLi and BLi+1. The capacitor of the memory cell, which is connected to the word lines WLi and WLi+1 respectively, is commonly connected to one plate line PLi.